Computer memory devices have increasingly dense architecture, as advances in technology allow for smaller and smaller components within each device. Each memory device thus has become more complicated for testing, as the memory to be tested has become more complex.
Within serial port memory devices, there may be increasing numbers of memory subparts and serial IO ports that require testing. The testing of such devices efficiently poses a significant challenge to manufacturers, who are commonly forced to free up more silicon area for memory cells instead of testing circuitry and to expend significant effort and expense in board testing.
Within this environment, manufacturers fabricate growing numbers of memory boards or devices, with pressure to reduce costs. For this reason, manufacturers are faced with issues regarding how to test multiple devices efficiently, while also accurately determining which of the tested memory devices actually contains a flaw and what kind of flaw is present.